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Datasheet No - PD97380 June 22, 2009
IRS2093MPbF
4 CH Digital Audio Amplifier Features
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Product Summary
Topology VOFFSET (max) IO+ & IO- (typical) Selectable deadtime DC offset OC protection delay Shutdown propagation delay Error amplifier open loop gain Half-Bridge and FullBridge +/- 100 V 0.5 A & 0.6 A 45/65/85/105ns <18 mV 500ns (max) 250ns (max) >60 dB
4 channel integrated analog input Class D audio amplifier drivers in a 48 pin MLPQ package Programmable over current protection Programmable dead-time generation Versatile protection control enabling latched, non-latched, or host controlled shutdown function Versatile input structure for self-oscillating PWM, external clock synchronization, or natural carrier based PWM modulations Start and stop click noise reduction Under voltage protection High noise immunity
Package
MLPQ48 (7x7mm, 0.50mm pitch)
Typical Connection
VREF
CSH4
VCC
COM
HO4
OCSET
HO3
VB4
VS4
VS3
NC
DT
CSH2
HO2
VB2
VS2
VS1
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HO1
DS
NC
NC
NC
NC
NC
13
14
15
16
17
18
19
20
21
22
23
24
37 38 39 40 41 42 43 44 45 46 47 48
(c) 2009 International Rectifier
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Table of Contents
Typical Connection Diagram Qualification Information Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Functional Block Diagram Input/Output Pin Equivalent Circuit Diagram Lead Definitions Lead Assignments Application Information and Additional Details Package Details Tape and Reel Details Part Marking Information Ordering Information
Page
1 4 5 6 7 10 11 12 13 14 16 17 18 19
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Description
The IRS2093 integrates four channels of high voltage, high performance Class D audio amplifier drivers with PWM modulators and protections. In conjunction with external MOSFET and external components, a complete 4 channel Class D audio amplifier can be realized. The IRS2093 is designed with floating analog inputs and protection control interface pin especially for half bridge topology. High and low side MOSFET are protected from over current conditions by a programmable bi-directional current sensing. Essential elements of PWM modulator section allow flexible system design. A small MLPQ48 package enhances the benefit of smaller size of Class D topology.
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Qualification Information
Qualification Level
Industrial Comments: This family of ICs has passed JEDEC's Industrial qualification. IR's Consumer qualification level is granted by extension of the higher Industrial level. MSL2, 260C (per IPC/JEDEC J-STD-020) Class I, Level A (per JESD78A) Yes
Moisture Sensitivity Level IC Latch-Up Test RoHS Compliant
Qualification standards can be found at International Rectifier's web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information.
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Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM; all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol VBn VSn VHon VCSHn VCCn VLOn VAA VSS VGND COM2 IIN-n VCSD VCOMPn VDS VDT VOCSET IAAZ ISSZ ICCZn IBSZn IOREF dVSn/dt dVSSn/dt Pd RthJA TJ TS TL Definition High side floating supply voltage High side floating supply voltage , n=1-4 High side floating output voltage, n=1-4 CSH pin input voltage, n=1-4 Low side fixed supply voltage , n=1-2 Low side output voltage, n=1-4 Floating input positive supply voltage Floating input negative supply voltage Floating input supply ground voltage Low side output supply return Inverting input current , n=1-4 SD pin input voltage COMP pin input voltage, n=1-4 DS pin input voltage DT pin input voltage OCSET pin input voltage Floating input positive supply zener clamp current (N t 2) input negative supply zener clamp current Floating (N t side supply zener clamp current, n=1-2 Low 2) Floating supply zener clamp current , n=1-4 Reference output current Allowable Vs voltage slew rate, n=1-4 Allowable Vss voltage slew rate , n=1-4 Maximum power dissipation @ TA +25C Thermal resistance, Junction to ambient Junction Temperature Storage Temperature Lead temperature (Soldering, 10 seconds)

Min. -0.3 VBn -15 VSn -0.3 VSn -0.3 -0.3 -0.3 (See IAAZ) -1 (See ISSZ) VSS -0.3 (See ISSZ) -0.3 VSS -0.3 VSS -0.3 VSS -0.3 -0.3 -0.3 -55 -
Max. 215 VBn +0.3 VBn +0.3 VBn +0.3 20 VCC2 +0.3 210 GND +0.3 VAA +0.3 (See IAAZ) +0.3 3 VAA +0.3 VAA +0.3 VAA +0.3 VCC +0.3 VCC+0.3 20 20 10 10 5 50 50 6.2 20 150 150 300
Units V V V V V V V V V V mA V V V V V mA mA mA mA mA V/ns V/ms W C/W C C C

IN-1-4 contains clamping diode to GND. VAA-VSS, Vcc1-COM, Vcc2-COM2, VB1-VS1, VB2-VS2, VB3-VS3 and VB4-VS4 contain internal shunt zener diodes. Please note that the voltage ratings of these can be limited by the clamping current. For the rising and falling edges of step signal of 10V. Vss=15V to 200V. According to JESD51-5. JEDEC still air chamber.
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Recommended Operating Conditions
For proper operation, the device should be used within the recommended conditions below. The Vs and COM offset ratings are tested with supplies biased at VAA-VSS=10V, VCC=12V and VB-VS=12V. All voltage parameters are absolute voltages referenced to COM; all currents are defined positive into any lead. Symbol Definition Min. Max. Units VBn VSn IAAZ ISSZ VSS VHOn VCC, VCC2 VLOn VGND VIN-n VCSD VCOMPn CCOMPn VDT IOREF VOCSET VCSHn dVss/dt fSW TA High side floating supply absolute voltage, n=1-4 High side floating supply offset voltage Floating input positive supply zener clamp current Floating input negative supply zener clamp current Floating input supply absolute voltage High side floating output voltage, n=1-4 Low side fixed supply voltage Low side output voltage, n=1-4 GND pin input voltage Inverting input voltage, n=1-4 CSD pin input voltage COMP pin input voltage, n=1-4 COMP pin phase compensation capacitor to GND, n=1-4 DT pin input voltage Reference output current to COM OCSET pin input voltage CSH pin input voltage, n=1-4 Allowable Vss voltage slew rate upon power-up Switching Frequency Ambient Temperature

VSn +10 1 1 0 Vs 10 0
VSS
VSn +14 200 11 11 200 VB 15 VCC2
VAA
V V mA mA V V V V V V V V nF V mA V V V/ms kHz C
VGND -0.5 VSS VSS 1 0 0.3 0.5 VSn -40
VGND +0.5 VAA VAA VCC 0.8 5 VBn 50 800 125
Logic operational for Vsn equal to -5V to +200V. Logic state held for Vsn equal to -5V to -VBSn. Nominal voltage for VREF is 5.1V. IOREF of 0.3 - 0.8mA dictates total external resistor value on VREF to be 6.3k to 16.7k ohm. GND input voltage is limited by IIN-n. Vss ramps up from 0V to 200V.
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Electrical Characteristics
VCC= VCC2=VBS1=VBS2,=VBS3=VBS4 =12V, VSS=VS1=VS2=VS3=VS4=COM=0V, VGND=5V, VAA=10V, CL=1nF and TA=25C unless otherwise specified. Definition Min Typ Max Units Test Conditions Symbol Low Side Supply 1 UVCC+ Vcc supply UVLO positive 8.4 8.9 9.4 V threshold UVCCVcc supply UVLO negative 8.2 8.7 9.2 V threshold UVCCHYS UVCC hysteresis 0.2 V IQCC_DT Low side quiescent current 3.3 6.6 mA VDT=VCC Low side zener diode clamp 19.0 20.4 21.6 V ICC1=5mA VCLAMPL1 voltage Low Side Supply 2 IQCC2 Low side quiescent current 2.4 5.0 mA VDT=COM Low side zener diode clamp VCLAMPL2 19.6 20.4 21.6 V ICC2=5mA voltage High Side Floating Supply High side well UVLO positive UVBS+n 8.0 8.5 9.0 V threshold, n=1-4 High side well UVLO negative UVBS-n 7.8 8.3 8.8 V threshold, n=1-4 UVBSHYSn UVBS hysteresis, n=1-4 0.2 V High side quiescent current, 0.5 1 mA IQBSn n=1-4 High to Low side leakage 50 A VBn=VSn =200V ILKHn current, n=1-4 High side zener diode clamp VCLAMPHn 14.7 15.3 16.2 V IBSn=5mA voltage, n=1-4 Floating Input Supply UVAA+ VA+, VA- floating supply UVLO 8.2 8.7 9.2 V GND pin floating positive threshold from VSS 7.7 8.2 8.7 V GND pin floating UVAAVA+, VA- floating supply UVLO negative threshold from VSS UVAAHYS UVAA hysteresis 0.5 V GND pin floating IQAA0 Floating Input positive quiescent 1 3 mA VCSD =VSS supply current IQAA10 Floating Input positive quiescent 12 25 mA supply current IQAA11 Floating Input positive quiescent 9 20 mA supply current IQAA2 Floating Input positive quiescent 20 40 mA VCSD =VSS+5V supply current ILKM Floating input side to Low side 50 A VAA=VSS=VGND= leakage current 100V VCLAMPM Floating supply zener diode IAA=5mA, 19.6 20.4 22.5 V clamp voltage VCSD =VSS Audio Input (VGND=0, VAA=5V, VSS=-5V, COM=COM2=VCC=VCC2=-5V, VS1=VS2=VS3=VS4=-5V, CSH1=CSH2=CHS3=CSH4=-5V, DT=OCSET=-5V) VOSn CHn input offset voltage, n=1-4 -18 0 18 mV IBINn CHn input bias current, n=1-4 40 nA GBWn CHn small signal bandwidth 9 MHz CCOMPn=1nF,
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Rfn=0 VCOMPn gmn GVn VNrmsn CHn OTA Output voltage, n=1-4 CHn OTA transconductance, n=14 CHn OTA gain, n=1-4 CHn OTA input noise voltage, n=1-4 VAA-1 60 100 250 VSS+1 V mS dB mVrms VIN-n=10mV
CHn slew rate, n=1-4 5 CHn common-mode rejection 60 ratio, n=1-4 PSRRn CHn supply voltage rejection ratio, 65 n=1-4 PWM comparator VthPWM PWM comparator threshold in (VAA COMP VSS)/2 fOTAn CHn COMP pin star-up local 0.7 1.0 oscillation frequency, n=1-4 Protection VREF Reference output voltage 4.8 5.1 VthOCLn CHn low side OC threshold in 1.1 1.2 Vsn, n=1-4 VthOCHn CHn high side OC threshold in 1.1+ Vs 1.2+ Vs VCSHn, n=1-4 0.4xVA 0.5xVA VthDS DS pin input threshold
A A
SRn CMRRn
-
V/us dB dB
BW=20kHz, Resolution BW=22Hz Fig.5 CCOMPn=1nF
1.5
V MHz VCSD =VSS+5V
5.4 1.3 1.3+ Vs 0.6xVA
A
V V V V V V A A ns
IOREF =0.5mA OCSET=1.2V Vs=200V, VSS =0V
CSD pin shutdown release 0.62xVAA 0.70xVAA 0.78xVAA threshold Vth2 CSD pin self reset threshold 0.26xVAA 0.30xVAA 0.34xVAA ICSD+ CSD pin discharge current 70 100 130 ICSDCSD pin charge current 70 100 130 tSDn CHn shutdown propagation delay 250 from VCSD > VSS + VthOCH to Shutdown tOCHn CHn propagation delay time from 500 VCSHn > VthOCHn to Shutdown, n=14 tOCLn CHn propagation delay time from 500 Vsn> VthOCL to Shutdown, n=1-4 Gate Driver Io+n CHn output high short circuit 0.5 current (Source) , n=1-4 Io-n CHn output low short circuit 0.6 current (Sink) , n=1-4 VOLn CHn low level out put voltage 0.1 LO - COM, HO - VS, n=1-4 VOHn CHn high level out put voltage 1.4 VCC - LO, VB - HO, n=1-4 Ton0n CHn high and low side turn-on 350 propagation delay, n=1-4 Toff0n CHn high and low side turn-off 325 propagation delay, n=1-4 Ton1n CHn high and low side turn-on 145 Vth1
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VCSD = VSS +5V VCSD = VSS +5V
ns
Fig.4
ns
Fig.3
A A V V ns ns ns
Vo=0V, PW<10S Vo=12V, PW<10S Io=0A
VDT = VCC, VDS=VAA VDT = VCC, VDS=VSS (c) 2009 International Rectifier
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Toff1n tr tf DT1n propagation delay, n=1-4 CHn high and low side turn-off propagation delay, n=1-4 Turn-on rise time Turn-off fall time CHn deadtime: LOn turn-off to HOn turn-on (DTLO-HO) & HOn turn-off to LnO turn-on (DTHO-LO) CHn deadtime: LOn turn-off to HOn turn-on (DTLO-HO) & HOn turn-off to LOn turn-on (DTHO-LO) CHn deadtime: LOn turn-off to HOn turn-on (DTLO-HO) & HOn turn-off to LOn turn-on (DTHO-LO) CHn deadtime: LOn turn-off to HOn turn-on (DTLO-HO) & HO turnoff to LOn turn-on (DTHO-LO)VDT= VDT4 DT mode select threshold 1 DT mode select threshold 2 DT mode select threshold 3 30 100 25 20 45 50 40 60 ns ns ns ns VDT>VDT1, VDT1>VDT> VDT2, VDT2>VDT> VDT3,
DT2n
45
65
85
ns
DT3n
65
85
105
ns
DT4n
85
105
145
ns
VDTVDT1 VDT2 VDT3
0.51xV 0.57xVc 0.63xV cc c cc 0.32xVcc 0.36xVcc 0.40xVcc 0.21xVcc 0.23xVcc 0.25xVcc
V V V
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Functional Block Diagram
COMP2 COMP4 COMP1 COMP3
37 36
CSD
GND
VAA
VSS
IN2
IN4
48
47
46
IN1
45
44
43
42
41
40
39
DS NC NC NC NC NC CSH2 VB2 HO2 VS2 VS1 HO1
IN3
38
OTA1
OTA2
OTA4
OTA3
VREF OCSET DT VCC COM NC CSH4 VB4 HO4 VS4 VS3 HO3
1
35
2
3
UVLO PROT COTRL
ENABLE
34
VREF 33 PWM 1 PWM 4 PWM 3 UVLO
4
PWM 2
32
5
LOW SIDE SUB
31
6
FLOATING INPUT
OCH 1 DT1 DT2 DT3 DT4
OCH 4
30
7
29
8
GD
GD GD
28
9
HIGH SIDE 2 HIGH SIDE 1
OCL 1 OCL 2
10
GD
OCL 4 OCL 3
27
HIGH SIDE 4 HIGH SIDE 3
26
11
GD
12
GD
25
GD
OCH 2
OCH 3
13
14
15
16
17
18
19
20
21
22
23
24
CSH1
VCC2
COM2
CSH3
LO1
NC
LO2
NC
LO4
LO3
VB1
: HIGH VOLTAGE LEVEL SHIFTER
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VB3
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GD
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Input/Output Pin Equivalent Circuit Diagrams
VAA ESD Diode IN20V Zener Diode ESD Diode VSS
ESD Diode 20 V Clamp ESD Diode ESD Diode 15 V Clamp ESD Diode
VB
HO
GND
VS
200 V
200 V
V CC VCC
LO
COM
COM
VAA
ESD Diode
VCC
ESD Diode
COMP, DS or CSD
ESD Diode
DT, VREF or OCSET COM
ESD Diode
VSS
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Lead Definitions
Pin #
1 2-6 7 8 9 10 11 12 13 14 15 16 17 18-19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
IN/OUT
IN IN IN OUT IN IN IN IN OUT OUT IN IN OUT OUT IN IN OUT IN IN OUT IN IN IN IN IN IN OUT OUT IN OUT IN IN IN IN IN OUT IN OUT IN/OUT
Symbol
DS NC CSH2 VB2 HO2 VS2 VS1 HO1 VB1 CSH1 LO1 LO2 VCC2 NC COM2 LO4 LO3 CSH3 VB3 HO3 VS3 VS4 HO4 VB4 CSH4 NC COM VCC DT OCSET VREF COMP3 IN3 COMP4 IN4 GND VSS VAA IN2 COMP2 IN1 COMP1 CSD
Description
Delay select input, referenced to VSS/VAA. H: with temp/co comp delay CH2 High side over current sensing input, referenced to VS2 CH2 High side floating supply CH2 High side output CH2 High side floating supply return CH1 High side floating supply return CH1 High side output CH1 High side floating supply CH1 High side over current sensing input, referenced to VS1 CH1 Low side output CH2 Low side output Low side gate drive supply Low side gate drive supply return CH4 Low side output CH3 Low side output CH3 High side over current sensing input, referenced to VS3 CH3 High side floating supply CH3 High side output CH3 High side floating supply return CH4 High side floating supply return CH4 High side output CH4 High side floating supply CH4 High side over current sensing input, referenced to VS4 Low side supply return Low side logic supply Input for programmable dead-time, referenced to COM Low side over current threshold setting, referenced to COM 5V reference output for setting OCSET CH3 Phase compensation input, comparator input CH3 Analog inverting input CH4 Phase compensation input, comparator input CH4 Analog inverting input Floating input supply return Floating input negative supply Floating input positive supply CH2 Analog inverting input CH2 Phase compensation input, comparator input CH1 Analog inverting input CH1 Phase compensation input, comparator input Shutdown timing capacitor, referenced to VSS
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Lead Assignments
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Application Information and Additional Details
VS
VthOCL
90% LO
tOCL
Figure 1 Switching Time Waveform Definitions
Figure 3 VS > VthOCL to Shutdown Waveform
VthOCH
Vth1
CSH
CSD
VS
90% HO/LO
HO
90%
tSD
tOCH
Figure 2 CSD to Shutdown Waveform Definitions Figure 4 VCSH > VthOCH to Shutdown Waveform
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Figure 5: OTA input noise voltage mesurent circuit
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Package Details: MLPQ 7X7
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Tape and Reel Details: MLPQ 7X7
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Part Marking Information
Pin 1 IR Logo
IRSxxxxM
Assembly Site Code
Part Number Date Code
CYWW? XXXX
Marking Code (Per Marking Spec) Lot Code (Prod mode - 4 digit SPN code)
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Ordering Information
Standard Pack Base Part Number Package Type Form IRS2093M MLPQ 48 7x7 Tube / Bulk Tape and Reel Quantity 52 3000 IRS2093MPBF IRS2093MTRPBF Complete Part Number
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied.
For technical support, please contact IR's Technical Assistance Center http://www.irf.com/technical-info/
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
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